1. Field of the Invention
The present invention relates to a method of forming a metal interconnect and, more particularly, to a method of forming a metal interconnect that substantially reduces the formation of intermetallic residue regions.
2. Description of the Related Art
A metal interconnect is a semiconductor structure that electrically connects together the individual devices on a semiconductor substrate to realize a desired circuit function. Multiple layers of metal are typically needed to provide the required interconnections, with current-generation integrated circuits often employing up to seven layers of metal.
FIG. 1 shows a cross-sectional view that illustrates a conventional semiconductor wafer 100. As shown in FIG. 1, wafer 100 includes a semiconductor substrate 110, and a metal interconnect 112 that is formed on substrate 110. Metal interconnect 112 electrically connects together a number of semiconductor devices that have been formed on substrate 110 to realize a desired circuit function.
As further shown in FIG. 1, metal interconnect 112 has a first layer of isolation material 114 that is formed on substrate 110, and first and second contacts 116 and 118 that are formed through isolation layer 114. Further, interconnect 112 also has a first metal (metal-1) trace 120 that is formed on isolation layer 114 and contact 116, and a metal-1 trace 122 that is formed on isolation layer 114 and contact 118. Contacts 116 and 118 make electrical connections with the devices formed in substrate 110, such as a source or a drain region of a MOS transistor, while metal-1 traces 120 and 122 make electrical connections with contacts 116 and 118, respectively.
In addition, interconnect 112 has a second layer of isolation material 130, known as an intermetal dielectric, that is formed on first isolation layer 114 and metal-1 traces 120 and 122, and first and second vias 132 and 134 that are formed through isolation layer 130. Interconnect 112 also has a second metal (metal-2) trace 136 that is formed on isolation layer 130 and via 132, and a metal-2 trace 138 that is formed on isolation layer 130 and via 134. Vias 132 and 134 make electrical connections with metal-1 traces 120 and 122, respectively, and metal-2 traces 136 and 138, respectively.
During fabrication, after isolation layer 114 has been formed on substrate 110, and contacts 116 and 118 have been formed through isolation layer 114, wafer 100 is placed into a plasma vapor deposition chamber. Once inside the chamber, a vacuum is established. After the vacuum has been established, a base layer of metal, such as aluminum/copper (0.5%), is plasma vapor deposited on isolation layer 114 and contacts 116 and 118.
Following the deposition of the base metal layer, the vacuum is maintained and a cap layer of metal is plasma vapor deposited on the base metal layer. After the cap metal layer has been formed, the cap metal layer and the underlying base metal layer are etched to form metal-1 trace 120 and metal-1 trace 122. The same steps are utilized to form metal-2 traces 136 and 138.
The cap metal layer can be implemented with, for example, titanium-tungsten. Other materials, such as titanium, tend to produce intermetallic residues when used. Intermetallic residues are regions of material that are formed when the material of the cap metal layer reacts with the material of the base metal layer. For example, when titanium is formed on a layer of aluminum-copper, intermetallic residue regions of aluminum-copper-titanium can be formed.
The intermetallic residue regions are difficult to remove using reactive ion etching (RIE) or magnetically enhanced reactive ion etching (MERIE) because the regions are etched at a rate that is much slower than the etch rates of the titanium layer and the aluminum-copper layer. Thus, at the end of the etch step that forms metal-1 traces 120 and 122, intermetallic residue regions, which are electrically conductive, remain in areas which are designed to be free of conductive material. The remaining intermetallic residue regions, in turn, can provide undesirable leakage paths as well as direct shorts.
One common approach to removing slower etching materials, overetching, produces poor results because an overetch that is sufficient to remove the residue regions is likely to severely compromise the interconnect quality and thus render the process non-manufacturable by normal quality metrics. Thus, the formation of intermetallic residue regions is an undesirable side effect when using titanium to form the cap metal layer.
The present invention provides a method of forming a metal interconnect that substantially reduces the formation of intermetallic residue regions. The method of the present invention forms a metal interconnect on a wafer that has a semiconductor substrate, and a first layer of isolation material that is formed on the surface of the substrate. The semiconductor substrate has a surface and an active region on the surface of the semiconductor substrate. The wafer also has a contact that is formed through the first layer of isolation material to make an electrical connection with the active region on the surface of the semiconductor substrate.
In accordance with the present invention, the method includes the step of depositing a base layer of metal on the first layer of isolation material and the contact in a first vacuum. The method also includes the step of forming a layer of insulation material on the base layer of metal. The method further includes the step of depositing a cap layer of metal on the layer of insulation material in a second vacuum.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.